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MTP Process Description
Author:管理员 Published:2012.11.6 Views: 11878
MTP Model m128x8

To Yan electronic generation embedded repeatedly rewritable non-volatile flash memory (Multi-Time Programmable MTP). The characteristics of the product in that the capacity is small but fast, and the space occupied by a small and short time required for the design. The to adopt of Laiyan electronic patent owner compatible logic technology products, under the premise of the tapeout process without increasing mask (MASK), a low-power, low-cost embedded flash memory IP for chip manufacturers. In addition, the product also uses electricity precise measurement technology, at any time to ensure that the memory contents of the logic gate not change the external factors greatly improve the stability and reliability of the memory IP. IP product as a low-end capacity required NRE price is relatively low, more attractive to many low-end chip manufacturers favor.

View of the product of the overall chip area occupied, and more is applied to the wireless information dissemination chip, precision machine tool positioning, Bluetooth system, LCD screen driver, and so on.



MTP Model m16kx8

The products use of Laiyan electronic second generation of IP chip design technology is more advanced an embedded repeatedly rewritable non-volatile flash memory (Multi-Time Programmable MTP) products. In based on m128x8 of, m16kx8 inheritance before all chip characteristics, such as electronic patent owner Laiyan compatible logic technology and increased read and write error correction, as well as more than 99% so that the available test coverage. In view of the greatly increased storage capacity of the product, in the past for the a small system firmware storage space trouble firmware design engineers have been liberated. Help enough fast storage space, firmware designers can add a variety of systems as much as possible to the desired function, making the end-product to be able to provide more services than ever. The main design of the products for the central processing unit (CPU / MCU) to provide high-speed cache read and write services.
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